Timing Solutions for Xilinx FPGAs and SoCs

By Silicon Labs 133

Timing Solutions for Xilinx FPGAs and SoCs

Silicon Labs offers a broad portfolio of frequency flexible ultra-low jitter timing products that enable hardware designers to simplify clock generation, distribution, and jitter attenuation with Xilinx FPGAs and SoCs with ample design margins, meeting stringent timing requirements for high-speed serial communications applications.

Silicon Labs clocks/jitter attenuators/network synchronizers use proprietary DSPLL and MultiSynth technologies to generate any combination of frequencies with ultra-low jitter, enabling some of the best clock tree integration in their class. Clock buffers provide low-jitter, low-skew clock distribution with integrated format/voltage level translation. PCIe® clocks/buffers combine Gen 1/2/3/4/5 compliance with on-chip series termination, simplifying design. XO/VCXOs are factory-customizable to any frequency with samples available in one to two weeks.

Portfolio Includes:
  • Network synchronizers
  • Jitter attenuating clocks
  • Clock generators
  • Clock buffers
  • PCIe clocks and buffers
  • Oscillators (XO/VCXO)

Silicon Labs timing solutions are widely used in several Xilinx evaluation boards and development kits, listed below:

Resources
  • Artix 7 (AC701) Reference Designs
  • Kintex 7 (KC705) Reference Designs
  • Virtex 7 (VC707) Reference Designs
  • Zynq SoC (ZC702) Reference Designs
  • Zynq SoC (ZC706) Reference Designs
  • Kintex Ultra Scale (KCU105) Reference Designs
  • Virtex Ultra Scale (VCU108) Reference Designs
  • Zynq 7000 (ZC702) Reference Designs
  • Zynq 7000 (ZC706) Reference Designs
  • Zync Ultra Scale+ MPSoC (ZCU102) Reference Designs
  • Zync Ultra Scale+ MPSoC (ZCU106) Reference Designs
  • Zync Ultra Scale+ RFSoC (ZCU111) Reference Designs

카테고리

Top