SN74LVC841ADWRG4

SN74LVC841ADWRG4
Mfr. #:
SN74LVC841ADWRG4
설명:
Latches 10B Bus Interface DType Latch
수명 주기:
이 제조업체의 새 제품입니다.
데이터 시트:
SN74LVC841ADWRG4 데이터 시트
배달:
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지불:
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ECAD Model:
추가 정보:
SN74LVC841ADWRG4 추가 정보 SN74LVC841ADWRG4 Product Details
제품 속성
속성 값
제조사:
텍사스 인스트루먼트
제품 카테고리:
래치
RoHS:
Y
회로 수:
1 Circuit
논리 유형:
D형 래치
논리 제품군:
LVC
극성:
비 반전
대기 전류:
10 uA
출력 라인 수:
10 Line
높은 수준의 출력 전류:
- 24 mA
저수준 출력 전류:
32 mA
전파 지연 시간:
7.5 ns at 2.7 V, 6.7 ns at 3.3 V
공급 전압 - 최대:
3.6 V
공급 전압 - 최소:
1.65 V
최소 작동 온도:
- 40 C
최대 작동 온도:
+ 85 C
패키지/케이스:
SOIC-24
포장:
기능:
투명한
키:
2.35 mm
길이:
15.4 mm
출력 유형:
3-State
유형:
D형
너비:
7.52 mm
상표:
텍사스 인스트루먼트
장착 스타일:
SMD/SMT
채널 수:
10 Channel
입력 라인 수:
10 Line
작동 공급 전압:
1.8 V, 2.5 V, 3.3 V
상품 유형:
래치
재설정 유형:
재설정 없음
공장 팩 수량:
1
하위 카테고리:
논리 IC
단위 무게:
0.021006 oz
Tags
SN74LVC841ADWR, SN74LVC841ADW, SN74LVC841AD, SN74LVC841A, SN74LVC84, SN74LVC8, SN74LVC, SN74LV, SN74L, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Bus Driver, LVC/LCX/Z Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24
***i-Key
IC D-TYPE LATCH SGL 3-ST 24SOIC
***as Instruments
This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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유효성
재고:
Available
주문 시:
1500
수량 입력:
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