LMK03328RHSR

Mfr. #:: LMK03328RHSR
설명:: Clock Synthesizer / Jitter Cleaner LMK03328 PLL/VCO CLOCK GENERATOR
수명 주기:: 이 제조업체의 새 제품입니다.
데이터 시트:: LMK03328RHSR 데이터 시트
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추가 정보:: LMK03328RHSR 추가 정보 LMK03328RHSR Product Details

제품 속성
속성 값

제조사:: 텍사스 인스트루먼트

제품 카테고리:: 클록 합성기 / 지터 클리너

RoHS:: Y

시리즈:: LMK03328

최소 작동 온도:: - 40 C

최대 작동 온도:: + 85 C

장착 스타일:: SMD/SMT

패키지/케이스:: WQFN-48

포장:: 릴

상표:: 텍사스 인스트루먼트

습기에 민감한:: 네

상품 유형:: 클록 합성기 / 지터 클리너

공장 팩 수량:: 2500

하위 카테고리:: 클록 및 타이머 IC

Tags: LMK0332, LMK033, LMK03, LMK0, LMK

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We provide 90-360 days warranty.

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

LMK03328RHSR 설명

***as Instruments: Ultra-low jitter clock generator family with two independent PLLs 48-WQFN -40 to 85

***ical: Clock Generator 1MHz to 300MHz-IN 1000MHz-OUT 48-Pin WQFN EP T/R

***ark: Lmk03328 Pll/Vco Clock Generator

*** Stop Electro: Processor Specific Clock Generator, 1000MHz, CMOS, PQCC48

***NS: The LMK03328 device is an ultra-low-noise clock generator with two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, reduces BOM cost and board area, and improves reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.

***AS INS: For each PLL, a differential/single-ended clock or crystal input can be selected as the PLL reference clock. The selected PLL reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency for the respective PLLs can be tuned between 4.8 GHz and 5.4 GHz. Both PLL/VCOs are equivalent in performance and functionality. Each PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. Each PLL has a post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.

***AS INSTRU: All the output channels can select the divided-down VCO clock from PLL1 or PLL2 as the source for the output divider to set the final output frequency. Some output channels can also independently select the reference input for PLL1 or PLL2 as an alternative source to be bypassed to the corresponding output buffers. The 8-bit output dividers support a divide range of 1 to 256 (even or odd), output frequencies up to 1 GHz, and output phase synchronization capability.

***AS INSTRUMENT: All output pairs are ground-referenced CML drivers with programmable swing that can be interfaced to LVDS or LVPECL or CML receivers with AC coupling. All output pairs can also be independently configured as HCSL outputs or 2x 1.8-V LVCMOS outputs. The outputs offer lower power at 1.8 V, higher performance and power supply noise immunity, and lower EMI compared to voltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional 3.3-V LVCMOS outputs can be obtained through the STATUS pins. This is an optional feature in case of a need for 3.3-V LVCMOS outputs and device status signals are not needed.

***AS USD: The device features self start-up from on-chip programmable EEPROM or pre-defined ROM memory, which offers multiple custom device modes selectable through pin control and can eliminate the need for serial programming. The device registers and on-chip EEPROM settings are fully programmable via I2C-compatible serial interface. The device slave address is programmable in EEPROM and LSBs are settable with a 3-state pin.

***AS INSRUMENT: The device provides two frequency margining options with glitch-free operation to support system design verification tests (DVT), such as standard compliance and system timing margin testing. Fine frequency margining (in ppm) can be supported by using a low-cost pullable crystal on the internal crystal oscillator (XO), and selecting this input as the reference to the PLL synthesizer. The frequency margining range is determined by the crystal’s trim sensitivity and the on-chip varactor range. XO frequency margining can be controlled through pin or I2C control for ease-of-use and high flexibility. Coarse frequency margining (in %) is available on any output channel by changing the output divide value through I2C interface, which synchronously stops and restarts the output clock to prevent a glitch or runt pulse when the divider is changed.

***AS INSTR: Internal power conditioning provide excellent power supply noise rejection (PSNR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from 3.3-V ± 5% supply and output blocks operate from 1.8-V, 2.5-V, 3.3-V ± 5% supply.

LMK03328RHSR 추가 정보

LMK03328 Ultra-Low Jitter Clock Generators: OMO Electronic LMK03328 Ultra-Low Jitter Clock Generators include two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution/fanout, and pin-selectable configuration states. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices. This reduces BOM cost and board area and improves reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces Bit Error Rate (BER) in high-speed serial links.

Market price

부분 #	설명	재고	가격
LMK03328RHSR DISTI # LMK03328RHSR-ND	ULTRA-LOW JITTER CLOCK GENERATOR RoHS: Compliant Min Qty: 2500 Container: Tape & Reel (TR)	Temporarily Out of Stock	2500:$9.9123
LMK03328RHSR DISTI # 27492977	Clock Generator 1MHz to 300MHz-IN 1000MHz-OUT 48-Pin WQFN EP T/R	2500	2500:$9.9120
LMK03328RHSR DISTI # LMK03328RHSR	PLL Clock Generator Dual 1MHz to 1000MHz 48-Pin WQFN T/R - Tape and Reel (Alt: LMK03328RHSR) RoHS: Compliant Min Qty: 2500 Container: Reel	Americas - 0	2500:$11.1900 5000:$10.5900 10000:$10.2900 15000:$9.8900 25000:$9.6900
LMK03328RHST DISTI # 595-LMK03328RHST	Clock Synthesizer / Jitter Cleaner Ultra-Low Jitter Clock Generator Family With Two Independent PLLs 48-WQFN -40 to 85 RoHS: Compliant	357	1:$19.0300 10:$17.5000 25:$16.5900 100:$14.7800 250:$14.0500 500:$13.1500
LMK03328RHSR DISTI # 595-LMK03328RHSR	Clock Synthesizer / Jitter Cleaner Ultra-Low Jitter Clock Generator Family With Two Independent PLLs 48-WQFN -40 to 85 RoHS: Compliant	0	1:$16.2600 10:$14.9500 25:$14.1800 100:$12.6300 250:$12.0100 500:$11.2300 1000:$10.3000

LMK03328RHSR

Step1:Vacuum Packaging with PL

Step2:Anti-Static Bag

Step3:Packaging Boxes

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes