SN74ALVC7803-25DLR

SN74ALVC7803-25DLR
Mfr. #:
SN74ALVC7803-25DLR
설명:
FIFO 512 X 18 CLOCKED FIFO
수명 주기:
이 제조업체의 새 제품입니다.
데이터 시트:
SN74ALVC7803-25DLR 데이터 시트
배달:
DHL FedEx Ups TNT EMS
지불:
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ECAD Model:
추가 정보:
SN74ALVC7803-25DLR 추가 정보 SN74ALVC7803-25DLR Product Details
제품 속성
속성 값
제조사:
텍사스 인스트루먼트
제품 카테고리:
선입선출
패키지/케이스:
SSOP-56
상표:
텍사스 인스트루먼트
장착 스타일:
SMD/SMT
작동 공급 전압:
3 V to 3.6 V
상품 유형:
선입선출
하위 카테고리:
메모리 및 데이터 저장
단위 무게:
0.024508 oz
Tags
SN74ALVC7803-2, SN74ALVC7803, SN74ALVC780, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Uni-Dir 512 x 18 56-Pin SSOP T/R
***i-Key Marketplace
FIFO, 512X18, 15NS, SYNCHRONOUS
***as Instruments
The SN74ALVC7803 FIFO is suited for buffering asynchronous data paths at 50-MHz clock rates and 13-ns access times and is designed for 3-V to 3.6-V VCC operation. The 56-pin shrink small-outline (DL) package offers greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when ,, and are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless of the ,, and levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.
부분 # 설명 재고 가격
SN74ALVC7803-25DLR
DISTI # SN74ALVC7803-25DLR-ND
IC MEMORY FIFO 512X18 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    SN74ALVC7803-25DLR
    DISTI # N/A
    FIFO 512 X 18 CLOCKED FIFO0
      SN74ALVC7803-25DLRFIFO, 512X18, 15ns, Synchronous, CMOS, PDSO56
      RoHS: Compliant
      1000
      • 1000:$6.9300
      • 500:$7.3000
      • 100:$7.6000
      • 25:$7.9300
      • 1:$8.5300
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      FIFO 16-Bit Edg-Trig D-Ty F-F W/3-State Otpt
      SN74ALVC7806-25DL

      Mfr.#: SN74ALVC7806-25DL

      OMO.#: OMO-SN74ALVC7806-25DL-TEXAS-INSTRUMENTS

      FIFO 16-Bit Edg-Trig D-Ty F-F W/3-State Otpt
      유효성
      재고:
      Available
      주문 시:
      3500
      수량 입력:
      SN74ALVC7803-25DLR의 현재 가격은 참고용이며 최상의 가격을 원하시면 판매팀 [email protected]으로 문의 또는 다이렉트 이메일을 보내주십시오.
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