CD74AC112M

CD74AC112M
Mfr. #:
CD74AC112M
설명:
Flip Flops Dual
수명 주기:
이 제조업체의 새 제품입니다.
데이터 시트:
CD74AC112M 데이터 시트
배달:
DHL FedEx Ups TNT EMS
지불:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
추가 정보:
CD74AC112M 추가 정보 CD74AC112M Product Details
제품 속성
속성 값
제조사:
텍사스 인스트루먼트
제품 카테고리:
플립플롭
RoHS:
Y
회로 수:
2
논리 제품군:
교류
논리 유형:
JK 네거티브 에지 트리거 플립플롭
극성:
반전/비반전
입력 유형:
CMOS, LVTTL
출력 유형:
미분
전파 지연 시간:
129 ns
높은 수준의 출력 전류:
- 24 mA
저수준 출력 전류:
24 mA
공급 전압 - 최소:
1.5 V
공급 전압 - 최대:
5.5 V
최소 작동 온도:
- 55 C
최대 작동 온도:
+ 125 C
장착 스타일:
SMD/SMT
패키지/케이스:
SOP-16
포장:
튜브
기능:
듀얼
키:
1.58 mm
길이:
9.9 mm
작동 온도 범위:
- 55 C to + 125 C
대기 전류:
4 uA
시리즈:
CD74AC112
너비:
3.91 mm
상표:
텍사스 인스트루먼트
채널 수:
2
입력 라인 수:
2
출력 라인 수:
1
작동 공급 전압:
1.5 V to 5.5 V
상품 유형:
플립플롭
재설정 유형:
설정, 재설정
공장 팩 수량:
40
하위 카테고리:
논리 IC
단위 무게:
0.004998 oz
Tags
CD74AC112M, CD74AC11, CD74AC1, CD74AC, CD74A, CD74, CD7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    S***v
    S***v
    BG

    I'm very satisfied

    2019-06-19
    O***b
    O***b
    SA

    Very fast shipping

    2019-02-04
***as Instruments
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and eset 16-SOIC -55 to 125
***ical
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SOIC Tube
***ark
LOGIC, DUAL JK FLIP-FLOP, 16SOIC
***i-Key
IC FF JK TYPE DUAL 1BIT 16SOIC
***AS INS
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
Logic Solutions
OMO Electronic Logic Solutions offers a full spectrum of logic functions and technologies from the mature to the advanced, including bipolar, BiCMOS, and CMOS. TI's process technologies offer the logic performance and features required for modern logic designs, while maintaining support for more traditional logic products.Learn More
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유효성
재고:
Available
주문 시:
1984
수량 입력:
CD74AC112M의 현재 가격은 참고용이며 최상의 가격을 원하시면 판매팀 [email protected]으로 문의 또는 다이렉트 이메일을 보내주십시오.
참고 가격(USD)
수량
단가
내선 가격
1
US$0.77
US$0.77
10
US$0.64
US$6.36
100
US$0.41
US$41.00
1000
US$0.33
US$328.00
2000
US$0.30
US$596.00
5000
US$0.28
US$1 385.00
10000
US$0.27
US$2 670.00
25000
US$0.26
US$6 425.00
시작
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