MC100LVEL34DG

Mfr. #:: MC100LVEL34DG
제조사:: ON Semiconductor
설명:: Clock Generators & Support Products HF ECL CLOCK GEN
수명 주기:: 이 제조업체의 새 제품입니다.
데이터 시트:: MC100LVEL34DG 데이터 시트
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HTML Datasheet:: MC100LVEL34DG Datasheet MC100LVEL34DG Datasheet (P4-P6)MC100LVEL34DG Datasheet (P7-P9)MC100LVEL34DG Datasheet (P10)
ECAD Model:

제품 속성
속성 값

제조사:: 온세미컨덕터

제품 카테고리:: 클록 생성기 및 지원 제품

RoHS:: Y

시리즈:: MC100LVEL34

유형:: 클록 생성기

최대 출력 주파수:: 1100 MHz

출력 수:: 3 Output

작동 공급 전압:: 4.2 V to 5.7 V

작동 공급 전류:: 39 mA

최소 작동 온도:: - 40 C

최대 작동 온도:: + 85 C

장착 스타일:: SMD/SMT

패키지/케이스:: SOIC-16

포장:: 튜브

상표:: 온세미컨덕터

지터:: 1 ps

상품 유형:: 클록 생성기

공장 팩 수량:: 48

하위 카테고리:: 클록 및 타이머 IC

단위 무게:: 0.023492 oz

Tags: MC100LVEL34, MC100LVEL3, MC100LVEL, MC100L, MC100, MC10, MC1

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

MC100LVEL34DG 설명

***et Europe: Clock Generator 16-Pin SOIC Rail

***ical: 3.3V ECL /2, /4, /8 Clock Generation Chip

***ser: Amplifiers- Audio HF ECL CLOCK GEN

***emi: 3.3 V ECL ÷·2, ÷·4, ÷·8 Divider

***th Star Micro: The MC100LVEL34 is a low skew 2 4 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other therefore the common output edges are all precisely aligned. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open. The common enable (EN bar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore all associated specification limits are referenced to the negative edge of the clock input. Upon start-up the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internaldividers as well as multiple LVEL34s in a system.

Market price

부분 #	제조	설명	재고	가격
MC100LVEL34DG DISTI # MC100LVEL34DGOS-ND	ON Semiconductor	IC CLOCK GEN ECL 2/4/8 16SOIC RoHS: Compliant Min Qty: 48 Container: Tube	Limited Supply - Call
MC100LVEL34DG	ON Semiconductor	RoHS: Not Compliant	856	1000:$5.3100 500:$5.5900 100:$5.8200 25:$6.0700 1:$6.5300
MC100LVEL34DTG DISTI # 863-MC100LVEL34DTG	ON Semiconductor	Clock Generators & Support Products 3.3V ECL Clock Generator RoHS: Compliant	97	1:$7.7400 10:$6.9900 25:$6.6700 100:$5.7900 250:$5.5300 500:$5.0400 1000:$4.3900
MC100LVEL34DR2G DISTI # 863-MC100LVEL34DR2G	ON Semiconductor	Clock Generators & Support Products HF ECL CLOCK GEN RoHS: Compliant	0	1:$7.7400 10:$6.9900 25:$6.6700 100:$5.7900 250:$5.5300 500:$5.0400 1000:$4.3900 2500:$4.2300
MC100LVEL34DG DISTI # 863-MC100LVEL34DG	ON Semiconductor	Clock Generators & Support Products HF ECL CLOCK GEN RoHS: Compliant	0
MC100LVEL34D DISTI # 863-MC100LVEL34D	ON Semiconductor	Clock Generators & Support Products 3.3V ECL Clock RoHS: Not compliant	0

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