CDC857-3DGGG4

Mfr. #:: CDC857-3DGGG4
설명:: IC 3.3V PLL CLK-DRVR 48-TSSOP
수명 주기:: 이 제조업체의 새 제품입니다.
데이터 시트:: CDC857-3DGGG4 데이터 시트
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추가 정보:: CDC857-3DGGG4 추가 정보 CDC857-3DGGG4 Product Details

제품 속성
속성 값

Tags: CDC857-3, CDC85, CDC8, CDC

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CDC857-3DGGG4 설명

***i-Key: IC 3.3V PLL CLK-DRVR 48-TSSOP

***ark: IC, PLL CLOCK DRIVER, 167MHZ, TSSOP-48; Clock IC Type:PLL Clock Driver; Frequency:167MHz; No. of Outputs:10; Supply Current:235mA; Supply Voltage Range:3V to 3.6V; Digital IC Case Style:TSSOP; No. of Pins:48 ;RoHS Compliant: Yes

***as Instruments: The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance state (3-state). Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. If AVCC is at GND and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized for operation from 0C to 85C.

Market price

부분 #	설명	재고	가격
CDC857-3DGGG4 DISTI # CDC857-3DGGG4-ND	IC 3.3V PLL CLK-DRVR 48-TSSOP RoHS: Compliant Min Qty: 80 Container: Tube	Limited Supply - Call
CDC857-3DGGG4 DISTI # 595-CDC857-3DGGG4	Phase Locked Loops - PLL Phase-Lock Loop Clock Drivers RoHS: Compliant	0

관련 상품

영상	부분 #	설명
	Mfr.#: CDC857-3DGGG4 OMO.#: OMO-CDC857-3DGGG4	Phase Locked Loops - PLL Phase-Lock Loop Clock Drivers
	Mfr.#: CDC857-2DGGRG4 OMO.#: OMO-CDC857-2DGGRG4	Clock Drivers & Distribution Phase-Lock Loop Clock Drivers
	Mfr.#: CDC857-2DGG OMO.#: OMO-CDC857-2DGG	Clock Drivers & Distribution Phase-Lock Loop Clock Drivers
	Mfr.#: CDC857-2 OMO.#: OMO-CDC857-2-1190	신규 및 오리지널
	Mfr.#: CDC857-20GGR OMO.#: OMO-CDC857-20GGR-1190	신규 및 오리지널
	Mfr.#: CDC857-2DGGRD4 OMO.#: OMO-CDC857-2DGGRD4-1190	신규 및 오리지널
	Mfr.#: CDC857-3DGG OMO.#: OMO-CDC857-3DGG-TEXAS-INSTRUMENTS	IC 3.3V PLL CLK-DRVR 48-TSSOP
	Mfr.#: CDC8573DGGR OMO.#: OMO-CDC8573DGGR-1190	신규 및 오리지널
	Mfr.#: CDC857B OMO.#: OMO-CDC857B-1190	신규 및 오리지널
	Mfr.#: CDC857-3DGGG4 OMO.#: OMO-CDC857-3DGGG4-TEXAS-INSTRUMENTS	IC 3.3V PLL CLK-DRVR 48-TSSOP

유효성

재고:: Available
주문 시:: 3000
수량 입력:

CDC857-3DGGG4의 현재 가격은 참고용이며 최상의 가격을 원하시면 판매팀 [email protected]으로 문의 또는 다이렉트 이메일을 보내주십시오.

참고 가격(USD)

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단가
내선 가격

1: ~~US$0.00~~; ~~US$0.00~~

10: ~~US$0.00~~; ~~US$0.00~~

100: ~~US$0.00~~; ~~US$0.00~~

500: ~~US$0.00~~; ~~US$0.00~~

1000: ~~US$0.00~~; ~~US$0.00~~

시작

CDC857-3 3
CDC85 14
CDC8 16
CDC 1309

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CDC857-3DGGG4

Step1:Vacuum Packaging with PL

Step2:Anti-Static Bag

Step3:Packaging Boxes

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes