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SN74LV166APWTG4

SN74LV166APWTG4
Mfr. #:
SN74LV166APWTG4
설명:
Counter Shift Registers Parallel Load 8B Shift Registers
수명 주기:
이 제조업체의 새 제품입니다.
데이터 시트:
SN74LV166APWTG4 데이터 시트
배달:
DHL FedEx Ups TNT EMS
지불:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
추가 정보:
SN74LV166APWTG4 추가 정보 SN74LV166APWTG4 Product Details
제품 속성
속성 값
제조사:
텍사스 인스트루먼트
제품 카테고리:
카운터 시프트 레지스터
RoHS:
Y
계산 순서:
직렬/병렬에서 직렬
회로 수:
1
비트 수:
8 bit
패키지/케이스:
TSSOP-16
논리 제품군:
LV
논리 유형:
CMOS
입력 라인 수:
9
전파 지연 시간:
23.3 ns, 18.9 ns, 11.9 ns
공급 전압 - 최대:
5.5 V
최소 작동 온도:
- 40 C
최대 작동 온도:
+ 85 C
포장:
릴
기능:
시프트 레지스터
너비:
4.4 mm
상표:
텍사스 인스트루먼트
장착 스타일:
SMD/SMT
출력 라인 수:
1
작동 공급 전압:
2.5 V, 3.3 V, 5 V
상품 유형:
카운터 시프트 레지스터
공장 팩 수량:
1
하위 카테고리:
논리 IC
단위 무게:
0.002169 oz
Tags
SN74LV166AP, SN74LV166, SN74LV16, SN74LV1, SN74LV, SN74L, SN74, SN7
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Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC SHIFT REGISTER SGL 8B 16TSSOP
***ark
Register Logic IC; Logic Family:LV-A; Supply Voltage Min:2V; Supply Voltage Max:5.5V; Package/Case:16-TSSOP; No. of Pins:16; Operating Temperature Range:-40°C to +85°C; Input Type:LVTTL; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
The 'LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation. The 'LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR\ overrides all other inputs, including CLK, and resets all flip-flops to zero. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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 신규 및 오리지널
유효성
재고:
Available
주문 시:
1500
수량 입력:
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