SN74ABT853DBRE4

SN74ABT853DBRE4
Mfr. #:
SN74ABT853DBRE4
설명:
Bus Transceivers 8 to 9-Bit Parity Bus Transceivers
수명 주기:
이 제조업체의 새 제품입니다.
데이터 시트:
SN74ABT853DBRE4 데이터 시트
배달:
DHL FedEx Ups TNT EMS
지불:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
추가 정보:
SN74ABT853DBRE4 추가 정보 SN74ABT853DBRE4 Product Details
제품 속성
속성 값
제조사:
텍사스 인스트루먼트
제품 카테고리:
버스 트랜시버
RoHS:
Y
논리 제품군:
74ABT
입력 레벨:
TTL
출력 레벨:
TTL
출력 유형:
3-State
높은 수준의 출력 전류:
- 32 mA
저수준 출력 전류:
64 mA
전파 지연 시간:
4.8 ns
공급 전압 - 최대:
5.5 V
공급 전압 - 최소:
4.5 V
최소 작동 온도:
- 40 C
최대 작동 온도:
+ 85 C
패키지/케이스:
SSOP-24
포장:
기능:
패리티 검사기가 있는 버스 트랜시버
키:
1.95 mm
길이:
8.2 mm
회로 수:
1
제품:
비씨모스
대기 전류:
24 mA
기술:
비씨모스
너비:
5.3 mm
상표:
텍사스 인스트루먼트
장착 스타일:
SMD/SMT
채널 수:
8
공급 전류 - 최대:
38 mA
작동 공급 전압:
4.5 V to 5.5 V
극성:
비 반전
상품 유형:
버스 트랜시버
공장 팩 수량:
1
하위 카테고리:
논리 IC
단위 무게:
0.059966 oz
Tags
SN74ABT853DB, SN74ABT853D, SN74ABT853, SN74ABT85, SN74ABT8, SN74AB, SN74A, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC TRANSCVR 8-9BIT INVERT 24SSOP
***as Instruments
The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR\) output indicates whether or not an error in the B data has occurred. The output-enable (OEA\ and OEB\) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR\ flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE\) and clear (CLR\) control inputs. When both OEA\ and OEB\ are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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유효성
재고:
Available
주문 시:
5000
수량 입력:
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