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7200L12TPG

7200L12TPG
Mfr. #:
7200L12TPG
제조사:
IDT
설명:
FIFO ASYNCHRONOUS FIFO
수명 주기:
이 제조업체의 새 제품입니다.
데이터 시트:
7200L12TPG 데이터 시트
배달:
DHL FedEx Ups TNT EMS
지불:
T/T Paypal Visa MoneyGram Western Union
HTML Datasheet:
7200L12TPG Datasheet7200L12TPG Datasheet (P4-P6)7200L12TPG Datasheet (P7-P9)7200L12TPG Datasheet (P10-P12)7200L12TPG Datasheet (P13-P14)
ECAD Model:
제품 속성
속성 값
제조사:
IDT(통합 장치 기술)
제품 카테고리:
선입선출
RoHS:
Y
데이터 버스 폭:
9 bit
버스 방향:
양방향
메모리 크기:
2 kbit
타이밍 유형:
비동기
조직:
256 x 9
회로 수:
1
최대 클록 주파수:
50 MHz
액세스 시간:
12 ns
공급 전압 - 최대:
5.5 V
공급 전압 - 최소:
4.5 V
공급 전류 - 최대:
80 mA
최소 작동 온도:
0 C
최대 작동 온도:
+ 70 C
패키지/케이스:
PDIP-28
포장:
튜브
시리즈:
7200L
상표:
IDT
장착 스타일:
구멍을 통해
상품 유형:
선입선출
공장 팩 수량:
14
하위 카테고리:
메모리 및 데이터 저장
단위 무게:
0.147798 oz
Tags
7200L12, 7200L1, 7200L, 7200, 720
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***roFlash
FIFO Mem Async Dual Depth/Width Uni-Dir 256 x 9 28-Pin PDIP Tube/Tray
***i-Key
IC MEM FIFO 256X9 12NS 28-PDIP
***pmh
IC FIFO ASYNC 512X9 15NS 28DIP
***et
FIFO Mem Async Dual Depth/Width Uni-Dir 512 x 9 28-Pin PDIP Tube
***i-Key
IC FIFO ASYNC 512X9 15NS 28DIP
*** Electronic Components
FIFO 512 x 9 AsyncFIFO 5.0V 9 Dual 12ns
***et
FIFO Mem Async Dual Depth/Width Uni-Dir 4K x 9 28-Pin PDIP Tube
***i-Key
IC FIFO ASYNCH 4KX9 15NS 28DIP
*** Electronic Components
FIFO 8K x 9 AsyncFIFO 5.0V Dual Port
***et
FIFO Mem Async Dual Uni-Dir 16 x 5 20-Pin PDIP Tube
***ark
FIFO Logic IC; FIFO Function:Asynchronous; Data Rate:40Mbps; Frequency:40MHz; Memory Organization - FIFO:16 x 5bit; Supply Voltage Range:4.5V to 5.5V; Logic Case Style:DIP; No. of Pins:20; Operating Temperature Range:0°C to +70°C
***as Instruments
This 80-bit memory uses advanced low-power Schottky technology and features high speed and fast fall-through times. It is organized as 16 words by 5 bits. A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates from 0 to 40MHz in a bit-parallel format, word by word. Data is written into memory on a low-to-high transition at the load clock (LDCK) input and is read out on a low-to-high transition at the unload clock (UNCK). The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the FULL\, EMPTY\, (FULL-2)\, and (FULL+2)\ output flags. The FULL\ output is low when the memory is full and high when it is not full. The (FULL-2)\ output is low when the memory contains 14 data words. The EMPTY\ output is low when the memory is empty and high when it is not empty. The (EMPTY+2)\ output is low when two words remain in memory. A low level on the reset (RST\) input resets the internal stack control pointers and also sets EMPTY\ low and sets FULL\, (FULL-2)\, and (EMPTY+2)\ high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK after either a RST\ pulse or from an empty condition causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction. The SN74ALS229B is characterized for operation from 0C to 70C.
부분 # 제조 설명 재고 가격
7200L12TPG
DISTI # 7200L12TPG-ND		Integrated Device Technology IncIC MEM FIFO 256X9 12NS 28DIP
RoHS: Compliant
Min Qty: 84
Container: Tube		Temporarily Out of Stock
  • 84:$6.4986
7200L12TPG
DISTI # 7200L12TPG		Integrated Device Technology IncFIFO Mem Async Dual Depth/Width Uni-Dir 256 x 9 28-Pin PDIP Tube/Tray - Bulk (Alt: 7200L12TPG)
RoHS: Compliant
Min Qty: 84
Container: Bulk		Americas - 0
  • 84:$5.6900
  • 112:$5.2900
  • 196:$4.9900
  • 420:$4.7900
  • 840:$4.5900
7200L12TPG
DISTI # 7200L12TPG		Integrated Device Technology IncFIFO Mem Async Dual Depth/Width Uni-Dir 256 x 9 28-Pin PDIP Tube/Tray (Alt: 7200L12TPG)
RoHS: Compliant
Min Qty: 1
Container: Tray		Europe - 0
  • 1:€5.8900
  • 10:€5.3900
  • 25:€5.1900
  • 50:€4.9900
  • 100:€4.7900
  • 500:€4.5900
  • 1000:€4.2900
7200L12TPG
DISTI # 972-7200L12TPG		Integrated Device Technology IncFIFO ASYNCHRONOUS FIFO
RoHS: Compliant		154
  • 1:$7.2400
  • 10:$6.6600
  • 25:$6.5300
  • 50:$6.5000
  • 100:$5.8300
  • 250:$5.6600
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Mfr.#: RK09K1130ACL

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 Potentiometers 50 KOhms 30%
유효성
재고:
152
주문 시:
2135
수량 입력:
7200L12TPG의 현재 가격은 참고용이며 최상의 가격을 원하시면 판매팀 [email protected]으로 문의 또는 다이렉트 이메일을 보내주십시오.
참고 가격(USD)
수량
단가
내선 가격
1
US$7.24
US$7.24
10
US$6.66
US$66.60
25
US$6.53
US$163.25
50
US$6.50
US$325.00
100
US$5.83
US$583.00
250
US$5.66
US$1 415.00
2021년부터 반도체 공급 부족으로 인해 아래 가격은 2021년 이전 정상 가격입니다. 확인을 위해 문의를 보내주세요.
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