SN74LV374ADGVR

SN74LV374ADGVR
Mfr. #:
SN74LV374ADGVR
설명:
Flip Flops Octal Edge-Trig D-Ty F-F W/3-State Otpt
수명 주기:
이 제조업체의 새 제품입니다.
데이터 시트:
SN74LV374ADGVR 데이터 시트
배달:
DHL FedEx Ups TNT EMS
지불:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
추가 정보:
SN74LV374ADGVR 추가 정보 SN74LV374ADGVR Product Details
제품 속성
속성 값
제조사:
텍사스 인스트루먼트
제품 카테고리:
플립플롭
RoHS:
Y
회로 수:
8
논리 제품군:
74LV
논리 유형:
D형 플립플롭
극성:
비 반전
입력 유형:
단일 종단
출력 유형:
단일 종단
전파 지연 시간:
19.3 ns
높은 수준의 출력 전류:
- 16 mA
저수준 출력 전류:
16 mA
공급 전압 - 최소:
2 V
공급 전압 - 최대:
5.5 V
최소 작동 온도:
- 40 C
최대 작동 온도:
+ 85 C
장착 스타일:
SMD/SMT
패키지/케이스:
TVSOP-20
포장:
기능:
D형 버스 인터페이스
키:
1.05 mm
길이:
5 mm
대기 전류:
20 uA
너비:
4.4 mm
상표:
텍사스 인스트루먼트
채널 수:
8
입력 라인 수:
2
출력 라인 수:
1
작동 공급 전압:
2 V to 5.5 V
상품 유형:
플립플롭
공장 팩 수량:
1
하위 카테고리:
논리 IC
단위 무게:
0.002123 oz
Tags
SN74LV374AD, SN74LV374A, SN74LV374, SN74LV37, SN74LV3, SN74LV, SN74L, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC D-TYPE POS TRG SNGL 20TVSOP
***ark
Flip-Flop Logic IC; Flip Flop Type:D; Trigger Type:Positive Edge; Output Type:Tri-State Non-Inverted; Supply Voltage Range:2V to 5.5V; Logic Case Style:TVSOP; No. of Pins:20; Operating Temperature Range:-40°C to +85°C ;RoHS Compliant: Yes
***as Instruments
The ’LV374A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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신규 및 오리지널
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유효성
재고:
Available
주문 시:
4500
수량 입력:
SN74LV374ADGVR의 현재 가격은 참고용이며 최상의 가격을 원하시면 판매팀 [email protected]으로 문의 또는 다이렉트 이메일을 보내주십시오.
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