SN74LS173ADRE4

SN74LS173ADRE4
Mfr. #:
SN74LS173ADRE4
설명:
Flip Flops 4-Bit D-type Reg With 3-State Outputs
수명 주기:
이 제조업체의 새 제품입니다.
데이터 시트:
SN74LS173ADRE4 데이터 시트
배달:
DHL FedEx Ups TNT EMS
지불:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
추가 정보:
SN74LS173ADRE4 추가 정보 SN74LS173ADRE4 Product Details
제품 속성
속성 값
제조사:
텍사스 인스트루먼트
제품 카테고리:
플립플롭
RoHS:
Y
회로 수:
1
논리 제품군:
74LS
논리 유형:
D형 레지스터
극성:
비 반전
입력 유형:
단일 종단
출력 유형:
단일 종단
전파 지연 시간:
30 ns
높은 수준의 출력 전류:
- 2.6 mA
저수준 출력 전류:
24 mA
공급 전압 - 최소:
4.75 V
공급 전압 - 최대:
5.25 V
최소 작동 온도:
0 C
최대 작동 온도:
+ 70 C
장착 스타일:
SMD/SMT
패키지/케이스:
SOP-16
포장:
기능:
D형 버스 인터페이스
키:
1.58 mm
길이:
9.9 mm
너비:
3.91 mm
상표:
텍사스 인스트루먼트
채널 수:
4
입력 라인 수:
2
출력 라인 수:
1
작동 공급 전압:
4.75 V to 5.25 V
상품 유형:
플립플롭
재설정 유형:
마스터 리셋
공장 팩 수량:
1
하위 카테고리:
논리 IC
단위 무게:
0.023492 oz
Tags
SN74LS173ADR, SN74LS173AD, SN74LS173, SN74LS17, SN74LS1, SN74LS, SN74L, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC D-TYPE POS TRG SNGL 16SOIC
***eco
4-BIT D-TYPE REGISTER WITH 3-STATE<AZ
***ark
Flip-Flop Logic IC; Logic Family:LS; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Package/Case:16-SOIC; No. of Pins:16; Operating Temperature Range:0°C to +70°C; Input Type:TTL; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
The '173 and 'LS173A 4-bit registers include D-type flip-flops featuring totem-pole 3-state outputs capable of driving highly capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G\1, G\2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table. The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of -55C to 125C. The SN74173 and SN74LS173A are characterized for operation from 0C to 70C.
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신규 및 오리지널
유효성
재고:
Available
주문 시:
4000
수량 입력:
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