 |  |  | |
| PartNumber | 74HC112DB,112 | 74HC112DB,118 | 74HC112PW,112 |
| Description | Flip Flops DUAL J-K NEG EDGE | Flip Flops DUAL J-K NEG EDGE | Flip Flops DUAL J-K NEG EDGE |
| Manufacturer | Nexperia | NXP Semiconductors | NXP Semiconductors |
| Product Category | Flip Flops | Logic - Flip Flops | Logic - Flip Flops |
| RoHS | Y | - | - |
| Number of Circuits | 2 | - | - |
| Logic Family | HC | - | - |
| Logic Type | J-K Negative Edge Triggered Flip-Flop | - | - |
| Polarity | Inverting/Non-Inverting | - | - |
| Input Type | Single-Ended | - | - |
| Output Type | Differential | Differential | Differential |
| Propagation Delay Time | 17 ns at 5 V | - | - |
| High Level Output Current | - 7.8 mA | - | - |
| Low Level Output Current | 7.8 mA | - | - |
| Supply Voltage Min | 2 V | - | - |
| Supply Voltage Max | 6 V | - | - |
| Minimum Operating Temperature | - 40 C | - | - |
| Maximum Operating Temperature | + 125 C | - | - |
| Mounting Style | SMD/SMT | - | - |
| Package / Case | SSOP-16 | - | - |
| Packaging | Tube | Tape & Reel (TR) Alternate Packaging | Tube Alternate Packaging |
| Function | JK Type | Set(Preset) and Reset | Set(Preset) and Reset |
| Height | 1.8 mm | - | - |
| Length | 6.4 mm | - | - |
| Quiescent Current | 4 uA | - | - |
| Width | 5.4 mm | - | - |
| Brand | Nexperia | - | - |
| Number of Channels | 2 | - | - |
| Number of Input Lines | 2 | - | - |
| Number of Output Lines | 1 | - | - |
| Operating Supply Voltage | 5 V | - | - |
| Product Type | Flip Flops | - | - |
| Reset Type | Set, Reset | - | - |
| Factory Pack Quantity | 78 | - | - |
| Subcategory | Logic ICs | - | - |
| Part # Aliases | 74HC112DB | - | - |
| Series | - | 74HC | 74HC |
| Type | - | JK Type | JK Type |
| Package Case | - | 16-SSOP (0.209", 5.30mm Width) | 16-TSSOP (0.173", 4.40mm Width) |
| Operating Temperature | - | -40°C ~ 125°C (TA) | -40°C ~ 125°C (TA) |
| Mounting Type | - | Surface Mount | Surface Mount |
| Voltage Supply | - | 2 V ~ 6 V | 2 V ~ 6 V |
| Frequency Clock | - | 71MHz | 71MHz |
| Number of Elements | - | 2 | 2 |
| Current Output High Low | - | 5.2mA, 5.2mA | 5.2mA, 5.2mA |
| Max Propagation Delay V Max CL | - | 30ns @ 6V, 50pF | 30ns @ 6V, 50pF |
| Current Quiescent | - | 4μA | 4μA |
| Number of Bits per Element | - | 1 | 1 |
| Trigger Type | - | Negative Edge | Negative Edge |
| Input Capacitance | - | 3.5pF | 3.5pF |
| 제조사 | 부분 # | 설명 | RFQ |
|---|---|---|---|
Nexperia |
74HC112DB,112 | Flip Flops DUAL J-K NEG EDGE | |
| 74HC112PW,118 | Flip Flops DUAL J-K NEG EDGE | ||
| 74HC11D,653 | Logic Gates TRP 3-INPUT AND GATE | ||
| 74HC11D-Q100J | Logic Gates 74HC11D-Q100/SO14/REEL 13" Q1/ | ||
| 74HC11D,652 | Logic Gates TRIPLE 3-IN AND GATE | ||
| 74HC11D/AUJ | Logic Gates Quad 2-input NAND gate | ||
| 74HC11D,652 | Logic Gates TRIPLE 3-IN AND GATE | ||
| 74HC11D,653 | IC GATE AND 3CH 3-INP 14SO | ||
| 74HC112DB,118 | Flip Flops DUAL J-K NEG EDGE | ||
| 74HC112PW,118 | Flip Flops DUAL J-K NEG EDGE | ||
| 74HC112DB,112 | Flip Flops DUAL J-K NEG EDGE | ||
| 74HC112PW,112 | Flip Flops DUAL J-K NEG EDGE | ||
| 74HC11D-Q100J | Logic Gates 74HC11D-Q100/SO14/REEL 13" Q1 | ||
| 74HC11D SOP3.9 | 신규 및 오리지널 | ||
| 74HC112DB-T | Flip Flops DUAL J-K NEG EDGE | ||
| 74HC112PW-T | Flip Flops DUAL J-K NEG EDGE | ||
| 74HC112D.652 | IC: digital, JK flip-flop, Channels:2, HC, SMD, SO16, Package: tube | ||
| 74HC112PW.112 | IC: digital, JK flip-flop, Channels:2, Inputs:5, HC, SMD, TSSOP16 | ||
| 74HC112D-T | Flip Flops DUAL J-K NEG EDGE | ||
| 74HC112D/SOP | 신규 및 오리지널 | ||
| 74HC112D652 | Now Nexperia 74HC112D - J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16 | ||
| 74HC112D653 | Now Nexperia 74HC112D - J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16 | ||
| 74HC112DB | Flip Flops DUAL J-K NEG EDGE | ||
| 74HC112DR SOP3.9 | 신규 및 오리지널 | ||
| 74HC112N652 | Now Nexperia 74HC112N - J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16 | ||
| 74HC112PW | - Bulk (Alt: 74HC112PW) | ||
| 74HC112PW112 | Now Nexperia 74HC112PW - J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, TSSOP16 | ||
| 74HC112PW118 | - Bulk (Alt: 74HC112PW118) | ||
| 74HC112PWR | 신규 및 오리지널 | ||
| 74HC113D | Dual JK NEG-Edge-Trig FF w/Preset | ||
| 74HC113N | Dual JK NEG-Edge-Trig FF w/Preset | ||
| 74HC114D | - Bulk (Alt: 74HC114D) | ||
| 74HC114N | Dual JK NEG-Edge-Trig FF w/pst/clr/clk | ||
| 74HC11ANS | 신규 및 오리지널 | ||
| 74HC112DR | 신규 및 오리지널 | ||
| 74HC112E | 신규 및 오리지널 | ||
| 74HC112N | - Bulk (Alt: 74HC112N) | ||
| 74HC11D+653 | AND Gate, HC/UH Series, 3-Func, 3-Input, CMOS, PDSO14 | ||
| 74HC11D/S200 | 신규 및 오리지널 | ||
| 74HC112FPEL-E | 신규 및 오리지널 | ||
| 74HC112P-E | 신규 및 오리지널 | ||
| 74HC112PW/S500118 | - Bulk (Alt: 74HC112PW/S500118) | ||
| 74HC112TELL-E | 신규 및 오리지널 | ||
| 74HC11D | AND GATE, 3I/P, SOIC-14, Logic Family / Base Number:74HC11, Logic Type:AND Gate, Output Current:5.2mA, No. of Inputs:3, Supply Voltage Min:2V, Supply Voltage Max:6V, Logic Case Style:SOIC, No. | ||
| 74HC11D-Q100118 | - Bulk (Alt: 74HC11D-Q100118) | ||
| 74HC11D-Q100653 | - Bulk (Alt: 74HC11D-Q100653) | ||
| 74HC11D/S400118 | 신규 및 오리지널 | ||
| 74HC11D118 | - Bulk (Alt: 74HC11D118) | ||
NXP Semiconductors |
74HC11D/AUJ | Logic Gates Quad 2-input NAND gate | |
| 74HC112N,652 | Flip Flops DUAL J-K NEG EDGE |